reactor charge vessel-empty permissive (graphical LD)¶


suite id	`g_vessel_empty_permissive`
domain	chemical_batch
language	LD-graphical
difficulty	medium
validation status	validated
origin	authored
license	CC-BY-4.0

Authored for this suite, modeling a feed/discharge valve interlock gated by vessel-empty confirmation

What is proved¶

From benchmarks/chemical_batch/g_vessel_empty_permissive/props.yaml. What each kind claims, and what it becomes on either route, is on The properties we prove.

id	kind	claim	requirement
`P1`	`mutual_exclusion`	never true together: `feed_valve`, `discharge_valve`	Feed and discharge valves must never be open together; feed requires the vessel confirmed empty.

Variants¶

file	expected verdict	violates	method
`clean.xml`	SAFE	none	expert
`bomb.xml`	VIOLATION	`P1`	fault-injection

Files¶

file	what it is	size	sha256
`benchmark.yml`	benchmark metadata	1.1 KB	`1a21de0bd970`
`bomb.xml`	ladder program, PLCopen XML	3.4 KB	`ffc3bc4e9601`
`clean.xml`	ladder program, PLCopen XML	3.0 KB	`31e4ba659d0c`
`props.yaml`	property file	0.2 KB	`263fee5405d7`

Structured text, derived¶

Read off the ladder graph by runner/ld_to_st.py: every rung's contacts and coils rewritten as IEC 61131-3 assignments, in the same series/parallel logic the PLCopen XML encodes. This is a reading aid, not a second source of expected verdicts; ESBMC verifies the ladder program shown above, never this rendering.

bomb.xmlclean.xml

PROGRAM g_vessel_empty_permissive_bomb
VAR_INPUT
    feed_cmd : BOOL;
    discharge_cmd : BOOL;
    vessel_empty : BOOL;
    maint : BOOL;
END_VAR

VAR_OUTPUT
    feed_valve : BOOL;
    discharge_valve : BOOL;
END_VAR


feed_valve := (((NOT discharge_cmd AND vessel_empty) AND feed_cmd) OR (feed_cmd AND maint));
discharge_valve := (discharge_cmd AND NOT vessel_empty);

END_PROGRAM

PROGRAM g_vessel_empty_permissive_clean
VAR_INPUT
    feed_cmd : BOOL;
    discharge_cmd : BOOL;
    vessel_empty : BOOL;
    maint : BOOL;
END_VAR

VAR_OUTPUT
    feed_valve : BOOL;
    discharge_valve : BOOL;
END_VAR


feed_valve := ((NOT discharge_cmd AND vessel_empty) AND feed_cmd);
discharge_valve := (discharge_cmd AND NOT vessel_empty);

END_PROGRAM

Recorded runs¶

A task can carry two routes. ld is ESBMC's ladder front end reading the program directly. via C is the same solver reached through Beremiz and MatIEC, which is the only route that reaches ST, IL, FBD and SFC; see How ESBMC-PLC works.

g_vessel_empty_permissive__bomb (props.yaml, expected VIOLATION): v8.4 VIOLATION
g_vessel_empty_permissive__clean (props.yaml, expected SAFE): v8.4 SAFE