timer latch mix (graphical LD twin)¶


suite id	`g_timer_latch_mix`
domain	elevator
language	LD-graphical
difficulty	medium
validation status	candidate
origin	authored
license	CC-BY-4.0
syntax pair of	`ld_timer_latch_mix`

Graphical twin of ld_timer_latch_mix: a timer drives a set coil and an acknowledgement drives the reset coil

What is proved¶

From benchmarks/elevator/g_timer_latch_mix/props.yaml. What each kind claims, and what it becomes on either route, is on The properties we prove.

id	kind	claim	requirement
`P1`	`invariant`	`!(Alarm && Ack)`	Acknowledge is dominant: the latched alarm and Ack never hold together.

Variants¶

file	expected verdict	violates	method
`program.xml`	SAFE	none	expert

Files¶

file	what it is	size	sha256
`benchmark.yml`	benchmark metadata	0.7 KB	`0ad6de7845b9`
`program.xml`	ladder program, PLCopen XML	3.3 KB	`9553ee0f55d6`
`props.yaml`	property file	0.2 KB	`b0fb335ad3a5`

Structured text, derived¶

Read off the ladder graph by runner/ld_to_st.py: every rung's contacts and coils rewritten as IEC 61131-3 assignments, in the same series/parallel logic the PLCopen XML encodes. This is a reading aid, not a second source of expected verdicts; ESBMC verifies the ladder program shown above, never this rendering.

program.xml

PROGRAM g_timer_latch_mix
VAR_INPUT
    Trig : BOOL;
    Ack : BOOL;
END_VAR

VAR_OUTPUT
    Alarm : BOOL;
END_VAR

VAR
    T0 : TON;
END_VAR


T0(IN:=Trig, PT:=T#30ms);
IF T0.Q THEN
    Alarm := TRUE;
END_IF;  (* 2 writers to Alarm: scan order decides which value survives *)
IF Ack THEN
    Alarm := FALSE;
END_IF;  (* 2 writers to Alarm: scan order decides which value survives *)

END_PROGRAM

Recorded runs¶

A task can carry two routes. ld is ESBMC's ladder front end reading the program directly. via C is the same solver reached through Beremiz and MatIEC, which is the only route that reaches ST, IL, FBD and SFC; see How ESBMC-PLC works.

timer_latch_mix (props.yaml, expected SAFE): master SAFE