conveyor interlock interlock (graphical LD)¶
| suite id | g_conveyor_interlock |
| domain | manufacturing |
| language | LD-graphical |
| difficulty | medium |
| validation status | validated |
| origin | authored |
| license | CC-BY-4.0 |
Authored for this suite to cover this domain with genuine control logic
What is proved¶
From benchmarks/manufacturing/g_conveyor_interlock/props.yaml. What each kind claims, and what it becomes on either route, is on The properties we prove.
| id | kind | claim | requirement |
|---|---|---|---|
P1 |
invariant |
!(conveyor && estop) |
The conveyor must never run while emergency-stop is active. |
Variants¶
| file | expected verdict | violates | method |
|---|---|---|---|
clean.xml |
SAFE | none | expert |
bomb.xml |
VIOLATION | P1 |
fault-injection |
Files¶
| file | what it is | size | sha256 |
|---|---|---|---|
benchmark.yml |
benchmark metadata | 1.0 KB | ddbd8e441ca9 |
bomb.xml |
ladder program, PLCopen XML | 3.1 KB | 45d48ef1ac73 |
clean.xml |
ladder program, PLCopen XML | 2.7 KB | 62c65df380f8 |
props.yaml |
property file | 0.2 KB | d7d55a88c756 |
Structured text, derived¶
Read off the ladder graph by runner/ld_to_st.py: every rung's contacts and coils rewritten as IEC 61131-3 assignments, in the same series/parallel logic the PLCopen XML encodes. This is a reading aid, not a second source of expected verdicts; ESBMC verifies the ladder program shown above, never this rendering.
Recorded runs¶
A task can carry two routes. ld is ESBMC's ladder front end reading the program directly. via C is the same solver reached through Beremiz and MatIEC, which is the only route that reaches ST, IL, FBD and SFC; see How ESBMC-PLC works.
g_conveyor_interlock__bomb(props.yaml, expectedVIOLATION): v8.4VIOLATIONg_conveyor_interlock__bomb__viacvia C (props.yaml, expectedVIOLATION): masterVIOLATIONg_conveyor_interlock__clean(props.yaml, expectedSAFE): v8.4SAFEg_conveyor_interlock__clean__viacvia C (props.yaml, expectedSAFE): masterSAFE