ftrig edge (graphical LD twin)¶


suite id	`g_ftrig_edge`
domain	packaging
language	LD-graphical
difficulty	easy
validation status	validated
origin	authored
license	CC-BY-4.0
syntax pair of	`ld_ftrig_edge`

Graphical PLCopen XML twin of the K-LD textual benchmark (syntax-coverage pair)

What is proved¶

From benchmarks/packaging/g_ftrig_edge/props.yaml. What each kind claims, and what it becomes on either route, is on The properties we prove.

id	kind	claim	requirement
`P1`	`invariant`	`!OneShot \|\| !Sig`	The falling-edge one-shot fires only when the signal is (now) low.

Variants¶

file	expected verdict	violates	method
`program.xml`	SAFE	none	expert

Files¶

file	what it is	size	sha256
`benchmark.yml`	benchmark metadata	0.7 KB	`1363fbfac011`
`program.xml`	ladder program, PLCopen XML	2.7 KB	`38824ff959f4`
`props.yaml`	property file	0.2 KB	`028ffa662763`

Structured text, derived¶

Read off the ladder graph by runner/ld_to_st.py: every rung's contacts and coils rewritten as IEC 61131-3 assignments, in the same series/parallel logic the PLCopen XML encodes. This is a reading aid, not a second source of expected verdicts; ESBMC verifies the ladder program shown above, never this rendering.

program.xml

PROGRAM g_ftrig_edge
VAR_INPUT
    Sig : BOOL;
END_VAR

VAR_OUTPUT
    Fall : BOOL;
    OneShot : BOOL;
    Sig_prev : BOOL;
END_VAR


Fall := (NOT Sig AND Sig_prev);
OneShot := Fall;
Sig_prev := Sig;

END_PROGRAM

Recorded runs¶

A task can carry two routes. ld is ESBMC's ladder front end reading the program directly. via C is the same solver reached through Beremiz and MatIEC, which is the only route that reaches ST, IL, FBD and SFC; see How ESBMC-PLC works.

ftrig_edge (props.yaml, expected SAFE): master VIOLATION
g_ftrig_edge__program__viac via C (props.yaml, expected SAFE): master SAFE