tp pulse (graphical LD twin)¶


suite id	`g_tp_pulse`
domain	packaging
language	LD-graphical
difficulty	medium
validation status	candidate
origin	authored
license	CC-BY-4.0
syntax pair of	`ld_tp_pulse`

Graphical twin of ld_tp_pulse. Expected VIOLATION: a pulse timer holds its output for the full width after the trigger drops, so Out does not imply Trig

What is proved¶

From benchmarks/packaging/g_tp_pulse/props.yaml. What each kind claims, and what it becomes on either route, is on The properties we prove.

id	kind	claim	requirement
`P1`	`invariant`	`!Out \|\| Trig`	The pulse output is asserted only in response to a trigger.

Variants¶

file	expected verdict	violates	method
`program.xml`	VIOLATION	none	expert

Files¶

file	what it is	size	sha256
`benchmark.yml`	benchmark metadata	0.8 KB	`eeee1a77eae7`
`program.xml`	ladder program, PLCopen XML	2.8 KB	`10366774a4a0`
`props.yaml`	property file	0.2 KB	`41a09daeebdc`

Structured text, derived¶

Read off the ladder graph by runner/ld_to_st.py: every rung's contacts and coils rewritten as IEC 61131-3 assignments, in the same series/parallel logic the PLCopen XML encodes. This is a reading aid, not a second source of expected verdicts; ESBMC verifies the ladder program shown above, never this rendering.

program.xml

PROGRAM g_tp_pulse
VAR_INPUT
    Trig : BOOL;
END_VAR

VAR_OUTPUT
    Out : BOOL;
END_VAR

VAR
    TP0 : TP;
END_VAR


TP0(IN:=Trig, PT:=T#30ms);
Out := TP0.Q;

END_PROGRAM

Recorded runs¶

A task can carry two routes. ld is ESBMC's ladder front end reading the program directly. via C is the same solver reached through Beremiz and MatIEC, which is the only route that reaches ST, IL, FBD and SFC; see How ESBMC-PLC works.

tp_pulse (props.yaml, expected VIOLATION): master VIOLATION